A wafer-level chip scale package (CSP) is a package for an integrated circuit that is substantially the size of the integrated circuit, which uses a wafer-level processing technique. Wafer-level CSP (WLCSP) processing techniques may apply one or more temporary photoresist (PR) layers that are removed at later stages of the process. WLCSP processing techniques may add one or more repassivation layers on the active side of the customer wafer, where at least part of the repassivation layer remains at the end of the process, as part of the final package. The PR layers and the repassivation layers are typically comprised of a photo-imageable or photosensitive material, although the PR layers and the repassivation layers may exhibit different film properties.
PR and repassivation layers may be imaged or processed to define openings or create vias. A via refers generally to a hole or an opening that extends through one or more layers of a chip package to expose an electrical contact. The openings or vias may be created by exposing the PR or repassivation layers to a certain type of light, for example ultraviolet (UV) light. A layer that is comprised of photosensitive polymer film will undergo a chemical reaction when exposed to UV light. This will allow subsequent process to strip a portion of the layer away, for example, revealing an electrical contact below.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present disclosure as set forth in the remainder of the present application with reference to the drawings.